Interconnects are used extensively in semiconductor devices and they typically comprise conductive lines with interconnect vias connecting several metallization levels. A major design concern preventing interconnect scaling and producing uniform conductive lines is the ability to fabricate interconnect vias near conductive line ends. Reducing the minimum distance between line ends for two separate conductive lines is advantageous for scaling and routing. The via-to-line overlay and critical dimension uniformity (CDU) limit how close interconnect vias may be placed near conductive line ends, which is a barrier to scaling.
With respect to interconnect vias formed near conductive line ends, it is essential to minimize both via center to via center spacing and distance between line ends for scaling. It is also important to maintain an offset distance between interconnect vias and conductive line ends, i.e., line end extensions. Line end extensions may provide a copper (Cu) supply to mitigate electromigration reliability concerns. The Cu supply in line end extensions may prevent voids from forming within conductive lines when an electrical current flows through the device. Accordingly, line end structures need to have the appropriate design and must be manufactured to address these concerns.